[Edited]VHDL counter won't run -

when num changes, counter should increase 1 num in sensitivity list. simulation says no. wonder what's wrong code. on quartus 9.0

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity tmp     port (         num : in std_logic_vector(3 downto 0);         counter : out std_logic_vector(3 downto 0);         clr : in std_logic     ); end tmp;  architecture ar of tmp     signal c : std_logic_vector(3 downto 0); begin     process(num, clr)     begin         if clr'event , clr = '1'             c <= "0000";         end if;         c <= c + 1;     end process;     counter <= c; end; 

if use directly counter instead of c , might you. try this

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity tmp     port (         num : in std_logic_vector(3 downto 0);         counter : out std_logic_vector(3 downto 0);         clr : in std_logic     ); end tmp;  architecture ar of tmp  begin     process(num, clr)     begin         if clr'event , clr = '1'             counter <= "0000";         end if;         counter <= counter + 1;     end process; end; 

codes out of asynchronous body run , counter stay same before