vhdl - how to understand (clk'event and clk='1') -

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since (clk'event , clk='1') commonly used describe rising edge event of clk signal, have following questions:

(1) how understand "and"? mean "then"?

(2) how (clk='1' , clk'event)? same above?

thanks!

  1. "and" means logical "and", in "both of these things should true expression return true".

  2. yes, logically equivalent.

having said this, should use in scenario rising_edge function, example if (rising_edge(clk)) then. , accompanying falling_edge function work correctly in more scenarios, , more readable.


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